View VSC7123_148618.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Features
* 802.3z Gigabit Ethernet-Compliant 1.25 Gb/s Transceiver * ANSI X3T11 Fibre Channel-Compliant 1.0625 Gb/s Transceiver * 0.98 to 1.36 Gb/s Full-Duplex Operation * 10-Bit TTL Interface for Transmit and Receive Data
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
* Automatic Lock-to-Reference * RX Cable Equalization * Analog/Digital Signal Detection * JTAG Access Port for Testability * Single +3.3V Supply, 650mW Typical * Packages: 64-Pin 10mm and 14mm PQFP and 10mm TQFP
General Description
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit (CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty clocks. The VSC7123 receiver detects "Comma" characters for frame alignment. An analog/digital signal detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher performance, lower cost replacement for the VSC7125 and VSC7135.
VSC7123 Block Diagram
10
R(0:9)
QD
Serial to Q Parallel D /10
QD 2:1
RX+ RX-
RCLK RCLKN COMDET ENCDET EWRAP SIGDET T(0:9)
10
Clock /20 Recovery Comma Detect Signal Detect Parallel to Serial
DQ
DQ
TX+ TX-
REFCLK
x10 Clock Multiply
NOT SHOWN: JTAG Boundary Scan
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 1
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Data Sheet
VSC7123
Functional Description
Clock Synthesizer The VSC7123 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip Phase Lock Loop (PLL) uses a single external 0.1F capacitor to control the Loop Filter. Serializer The VSC7123 accepts TTL input data as a parallel 10-bit character on the T(0:9) bus, which is latched into the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL differential outputs at a baud rate that is 10 times the frequency of the REFCLK, with bit T0 transmitted first. User data should be encoded using 8B/10B block code or equivalent. Transmission Character Interface An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the VSC7123 corresponds to a transmission character. This mapping is illustrated in Figure 1. Figure 1: Transmission Order and Mapping of an 8B/10B Character
Parallel Data Bits 8B/10B Bit Position Comma Character
T9 j X
T8 h X
T7 g X
T6 f 1
T5 i 1
T4 e 1
T3 d 1
T2 c 1
T1 b 0
T0 a 0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery The VSC7123 accepts differential high-speed serial inputs on the RX+/RX- pins, extracts the clock and retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol Interference which may be present in the incoming data. The serial bit stream should be encoded to provide DC balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within +200 ppm of 10 times the REFCLK frequency. For example, Gigabit Ethernet systems would use 125MHz oscillators with a +100ppm accuracy resulting in +200 ppm between VSC7123 pairs. Deserializer The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7123 provides complementary TTL recovered clocks, RCLK and RCLKN, which are 1/20th of the serial baud rate. The clocks are generated by dividing down the high-speed recovered clock, which is phase-locked to the serial data. The
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. If serial input data is not present or does not meet the required baud rate, the VSC7123 will continue to produce a recovered clock, allowing downstream logic functionality to continue. Under these circumstances, the RCLK/RCLKN output frequency differ from its expected frequency by no more than +1%.
Word Alignment The VSC7123 provides 7-bit comma character recognition and data word alignment. Word synchronization is enabled by asserting ENCDET HIGH. When synchronization is enabled, the receiver examines the recovered serial data for the presence of the "Comma" character. This pattern is "0011111XXX", where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which are defined for synchronization purposes. Improper alignment of the comma character is defined as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that R0...R6 = "0011111." 2) The comma straddles the boundary between two 10-bit transmission characters. 3) The comma is properly aligned but occurs in the received character presented during the rising edge of RCLK rather than RCLKN. When ENCDET is HIGH and an improperly aligned comma is encountered, the recovered clock is stretched (never slivered) so that the comma character and recovered clocks are properly aligned to R(0:9). This results in proper character and word alignment. When the parallel data alignment changes in response to a improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. Additionally, the first Comma pattern may also be lost or corrupted. Subsequent data will be output correctly and properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. When encountering a comma character, COMDET is driven HIGH. The COMDET pulse is presented simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The COMDET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected and no phase adjustment is necessary. Figure 2 illustrates the position of the COMDET pulse in relation to the comma character on R(0:9). Figure 3 shows the case where the K28.5 is detected, but it is misaligned so a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process.
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 3
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Figure 2: Detection of a Properly Aligned Comma Character
Data Sheet
VSC7123
RCLK RCLKN
COMDET
R(0:9)
K28.5
TChar
TChar
TChar
TChar: 10-bit transmission character
Figure 3: Detection
Receiving Two Consecutive K28.5+TChar Transmission Words Clock Stretching
RCLK RCLKN
COMDET
R(0:9)
Potentially Corrupted
K28.5
TChar
TChar
TChar
K28.5
TChar
TChar: 10-bit transmission character
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Signal Detection The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine if the incoming signal contains valid data. SIGDET is updated every four RCLKs. If during the current period, all the four criteria are met, SIGDET will be HIGH during the next 4 RCLK period. If during the current period, any of the four criteria is not met, SIGDET will be LOW during the next 4 RCLK period.
1) Analog transition detection is performed on the input to verify that the signal swings are of adequate amplitude. The RX+/- input buffer contains a differential voltage comparator which will go HIGH if the differential peak-to-peak amplitude is greater than 400mV or LOW if under 200mV. If the amplitude is between 200mV and 400mV, the output is indeterminate. 2) Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current RCLK interval, the SIGDET output will go LOW during the next four RCLK interval. 3) Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current RCLK interval, the SIGDET output will go LOW during the next four RCLK interval. 4) Data on R(0:9) is monitored for K28.5- (0011111010). Unlike previous patterns, the interval during which a K28.5- must occur is 64K+24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data will contain a K28.5- character during any period of this length. If a K28.5- is not detected during the monitoring period, SIGDET will go LOW during the next period. The behavior of SIGDET is affected by EWRAP and ENCDET as shown in Table 1.
Table 1: Signal Detect Behavior EWRAP
0 0 1 1
ENCDET
0 1 0 1
COMDET
Disabled Enabled Disabled Enabled
Transition Detect
Enabled Enabled Enabled Enabled
All Zeros/ All Ones
Enabled Enabled Disabled Disabled
K28.5 Presence
Enabled Disabled Disabled Disabled
Mode
Normal SIGDET ignores commas Rollback Loopback
Note: COMDET, RCLK, RCLKN and R(0:9) are unaltered by SIGDET.
JTAG Access Port A JTAG Access Port is provided to assist in board-level testing. Through this port, most pins can be accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is available in "VSC7123/VSC7133 JTAG Access Port Functionality."
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 5
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Figure 4: Transmit Timing Waveforms
Data Sheet
VSC7123
REFCLK
T1 T2
T(0:9)
Data Valid
Data Valid
Data Valid
Table 2: Transmit AC Characteristics Parameters
T1 T2 TSDR,TSDF TLAT
Description
T(0:9) Setup time to the rising edge of REFCLK T(0:9) hold time after the rising edge of REFCLK TX+/TX- rise and fall time Latency from rising edge of REFCLK to T0 appearing on TX+/TX-
Min
1.5 1.0 -- 8bc
Typ
-- -- -- --
Max
-- -- 300 8bc+ 4ns
Units
ns ns ps ns
Conditions
Measured between the valid data level of T(0:9) to the 1.4V point of REFCLK.
20% to 80%, 50 load to VDD-2.0. bc = Bit clocks ns = Nano second
Transmitter Output Jitter Allocation
RJ DJ Random jitter (RMS) Serial data output deterministic jitter (pk-pk) -- -- 5 30 8 80 ps. ps. Measured at SO+/-, 1 sigma deviation of 50% crossing point. IEEE 802.3Z Clause 38.68, tested on a sample basis.
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Figure 5: Receive Timing Waveforms
T4
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
RCLK
T3
RCLKN
T1 T2
Data Valid
R(0:9)
Data Valid
Data Valid
Table 3: Receive AC Characteristics Parameters
T1 T2 T3 T4 TR, TF RLAT TLOCK(1)
Description
TTL Outputs Valid prior to RCLK/RCLKN rise TTL Outputs Valid after RCLK or RCLKN rise Delay between rising edge of RCLK to rising edge of RCLKN Period of RCLK and RCLKN R(0:9), COMDET, SIGDET, RCLK and RCLKN rise and fall time Latency from RX to R(0:9) Data acquisition lock time
Min.
4.0 3.0 3.0 2.0 10 x TRX -500 1.98 x TREFCLK -- 12 bc + 1 ns --
Max.
-- -- -- -- 10 x TRX +500 2.02 x TREFCLK 2.4 13 bc + 9 ns 1400
Units
ns ns ps ps ns bc ns bc
Conditions
At 1.0625Gb/s At 1.25Gb/s At 1.0625Gb/s At 1.25Gb/s TRX is the bit period of the incoming data on Rx. Whether or not locked to serial data. Between VIL(MAX) and VIH(MIN), into 10pf load. bc = bit clock ns = nano second 8B/10B IDLE pattern. bc = bit clocks
NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3.
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 7
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Figure 6: REFCLK Timing Waveforms
TL TH
Data Sheet
VSC7123
REFCLK
VIH(MIN) VIL(MAX)
TR TF
Table 4: Reference Clock Requirements Parameter
FR
Description
Frequency Range
Min
98
Max
136
Units
MHz
Conditions
Range over which both transmit and receive reference clocks on any link may be centered. Maximum frequency offset between transmit and receive reference clocks on one link. Measured at 1.5V Between VIL(MAX) and VIH(MIN)
FO DC TR,TF
Frequency Offset REFCLK duty cycle REFCLK rise and fall time
-200 35 --
200 65 1.5
ppm % ns
Page 8
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Figure 7: Parametric Measurement Information
Serial Input Rise and Fall Time
80% 20%
TTL Input and Output Rise and Fall Time
VIH(MIN)
VIL(MIN)
TR
TF
TR
TF
Receiver Input Eye Diagram Jitter Tolerance Mask
Bit Time
Amplitude
24% Minimum Eye Width%
Parametric Test Load Circuit Serial Output Load TTL AC Output Load
Z0 = 75W
50 or 75W
10pF
VDD - 2.0V
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 9
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Figure 8: Input Structures
VDDD VDDD
Data Sheet
VSC7123
3K
INPUT INPUT
4K
3K GND
INPUT
4K GND
TTL Inputs (not REFCLK)
VDD
+3.3 V
High-Speed Input (RX+/RX-)
12.6K
VDDP
VDDD
REFCLK
9.3K 12.6K 9.3K GND
TX+ TX-
GND
High-Speed Outputs (TX+/-)
REFCLK TTL Input
VDDT
OUTPUT
VSST
VSSD
TTL Outputs
Page 10
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
DC Characteristics (over recommended operating conditions)
Parameters Description Min
2.4 -- 2.0 0 -- -- 1200 1000 300 3.14 -- -- --
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Typ
-- -- -- -- 50 -- -- -- -- -- 650 190 --
Max
-- 0.5 5.5 0.8 500 -500 2200 2200 2600 3.47 900 260 100
Units
V V V V A A mVp-p mVp-p mVp-p V mW mA mA
Conditions
VOH VOL VIH VIL IIH IIL
VOUT75(1) VOUT50(1) VIN(1)
Output HIGH voltage (TTL) Output LOW voltage (TTL) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) TX output differential peakto-peak voltage swing TX output differential peakto-peak voltage swing RX Input differential peakto-peak input sensitivity Supply voltage Power dissipation Supply current (all supplies) Analog supply current
IOH = -1.0 mA IOL = +1.0 mA 5V Tolerant Inputs -- VIN = 2.4V VIN = 0.5V 75 to VDD - 2.0V (TX+) - (TX-) 50 to VDD - 2.0V (TX+) - (TX-) Internally biased to VDD/2 (RX+) - (RX-) 3.3V5% Outputs open, VDD = VDD max Outputs open, Case temp = 95oC, VDD = VDD max
VDD
PD IDD IDDA
VDDA = VDDA max
NOTE: (1) Refer to Application Note, AN-37, for differential measurement techniques.
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 11
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Data Sheet
VSC7123
Absolute Maximum Ratings (1)
Power Supply Voltage, (VDD) ................................................................................................................ -0.5V to +4V DC Input Voltage (PECL inputs)................................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs) ........................................................................................................... -0.5V to +5.5V DC Output Voltage (TTL outputs) ............................................................................................ -0.5V to VDD + 0.5V Output Current (TTL outputs) .................................................................................................................... +50mA Output Current (PECL outputs)................................................................................................................... +50mA Case Temperature Under Bias .......................................................................................................... -55oC to +125oC Storage Temperature.......................................................................................................................... -65oC to +150oC
Recommended Operating Conditions
Power Supply Voltage, (VDD) ................................................................................................................+3.3V+5% Operating Temperature Range ............................................................. 0oC Ambient to +95oC Case Temperature
Note: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC7123 is rated to the following ESD voltages based on the human body and charge device models: 1. All pins are rated at or above 1000V (charge device model). 2. All pins are rated at or above 2000V (human body model).
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Package Pin Descriptions
Figure 9: Pin Diagram (Top View)
VDDD TRSTN VDDD
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
VDDD
VDDP
VDDP
VSSD
VSSD
VSSD
TMS
TX+
N/C
63 VSSD T0 T1 T2 VDDD T3 T4 T5 T6 VDDD T7 T8 T9 VSSD VSSA CAP0 15 17 19 13 11 9 7 5 3 1
61
59
57
55
53
RX-
TX-
51
49 TDI 47 COMDET VSST 45 R0 R1 43 R2 VDDT
TCK
RX+
VSC7123
41
R3 R4
39
R5 R6
37
VDDT R7 R8 R9
35
21
23
25
27
29
31
33
VSST
SIGDET
CAP1
VDDA
TDO
EWRAP
REFCLK
ENCDET
RCLKN
RCLK
VDDD
VDDD
Table 5: Pin Identifications Pin #
2,3,4,6 7,8,9,11 12,13 22
Name
T0,T1,T2,T3 T4,T5,T6,T7 T8,T9 REFCLK
Description
INPUTS - TTL: 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK. The data bit corresponding to T0 is transmitted first. INPUT - TTL: This rising edge of this clock latches T(0:9) into the input register. It also provides the reference clock, at one tenth the baud rate to the PLL.
VDDD
VDDT
VSSD
VSSD
VSST
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 13
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Pin #
62, 61 45,44,43,41 40,39,38,36 35,34 19
Data Sheet
VSC7123
Description
Name
TX+, TXR0,R1,R2,R3 R4,R5,R6,R7 R8,R9 EWRAP
OUTPUTS - Differential PECL (AC-coupling recommended): These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. OUTPUTS - TTL: 10-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK and RCLKN. R0 is the first bit received on RX+/RX-. INPUT - TTL: LOW for normal operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled. TX+ is held HIGH and TX- is held LOW. INPUTS - Differential PECL (AC-coupling recommended): The serial receive data inputs selected when EWRAP is LOW. Internally biased to VDD/2, with 3.3K resistors from each input pin to VDD and GND. OUTPUT - Complementary TTL: Recovered clocks derived from 1/20th of the RX+/- data stream. Each rising transition of RCLK or RCLKN corresponds to a new word on R(0:9). INPUT - TTL: Enables COMDET and word resynchronization when HIGH. When LOW, keeps current word alignment and disables COMDET. OUTPUT - TTL: This output goes HIGH for half of an RCLK period to indicate that R(0:9) contains a comma character (`0011111XXX'). COMDET will go HIGH only during a cycle when RCLKN is rising. COMDET is enabled by ENCDET being HIGH. OUTPUT - TTL SIGnal DETect. This output goes HIGH when the RX input contains a valid Fibre Channel or Gigabit Ethernet signal. A LOW indicates an invalid signal. ANALOG: Differential capacitor for the CMU's VCO, 0.1 F nominal. INPUT - TTL: JTAG clock input. Not normally connected. INPUT - TTL: JTAG data input. Not normally connected. INPUT - TTL: JTAG mode select input. Normally tied to VDDD INPUT - TLL: JTAG reset input. Tie to VSSD for normal operation. OUTPU - TTL: JTAG data output. Normally tri-stated. Analog Power Supply Analog Ground Digital Logic Power Supply Digital Logic Ground TTL Output Power Supply TTL Output Ground PECL I/O Power Supply No internal connection
54, 52
RX+, RXRCLK, RCLKN ENCDET
31, 30
24
47
COMDET
26 16, 17 49 48 55 56 27 18 15 5,10,20,23 28,50,57,59 1,14,21,25 51,58,64 29, 37, 42 32, 33, 46 60,63 53
SIGDET CAP0, CAP1 TCK TDI TMS TRSTN TDO VDDA VSSA VDDD VSSD VDDT VSST VDDP N/C
Page 14
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Package Information: 64-pin PQFP
F G
64 49 48 1
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Item
A A2 E F G I H H I J K
10mm
2.45 2.00 0.22 13.20 10.00 13.20 10.00 0.88 0.50
14mm
2.35 2.00 0.35 17.20 14.00 17.20 14.00 0.88 0.80
Tolerance
MAX +0.10/-0.05 0.05 0.25 0.10 0.25 0.10 +0.15/-0.10 BASIC
16 33
17
10 TYP
o
32
A
A2
100 TYP
K
0.30 RAD. TYP.
A
0.20 RAD. TYP.
STANDOFF
0.25 MAX.
0.17 MAX. 0.25 J
0o- 8o
0.102 MAX. LEAD COPLANARITY
E NOTES: Drawing not to scale. All units in mm unless otherwise noted.
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 15
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Data Sheet
VSC7123
Package Information: 64-pin TQFP
F G
64 49
Item
A A1
48
10 mm
1.20 0.10 1.00 0.22 12.00 10.00 12.00 10.00 0.60 0.50 3.80 3.80
Tolerance
MAX 0.05 0.05 0.05 BASIC BASIC BASIC BASIC 0.15 BASIC BASIC BASIC
1
A2 E F
L
M
G I H H I J
16 33
K L M
17
11/13o 8 PLACES
32
A
A2
K
0.08/0.20 R
A
0.08 R MIN
STANDOFF A1
0.09/0.20 0.25 J
0o- 7o
0.08 MAX. LEAD COPLANARITY
E NOTES: Drawing not to scale. All units in mm unless otherwise noted.
Page 16
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01
VE
IT Y OC L
TM
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Package Thermal Considerations
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
The VSC7123 is packaged in a 14mm, thermally-enhanced PQFP with an internal heat spreader a 10 mm, thermally enhanced PQFP and a 10mm cavity-down, exposed pad TQFP. These packages use industry-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages is shown in Figure 10.
Figure 10: PQFP Package Cross Section
Plastic Molding Compound
Internal Heat Spreader Insulator
Lead
Table 6: Thermal Resistance
Symbol jc ca ca-100 ca-200 ca-400 ca-600
Bond Wire
Die
Description Thermal resistance from junction-to-case Thermal resistance from case-to-ambient in still air including conduction through the leads. Thermal resistance from case-to-ambient with 100 LFM airflow Thermal resistance from case-to-ambient with 200 LFM airflow Thermal resistance from case-to-ambient with 400 LFM airflow Thermal resistance from case-to-ambient with 600 LFM airflow
10mm PQFP 10 50 41 37 32 28
14mm PQFP 9.5 29 26 24 21 18
10mm TQFP 7.0 40 38 35 33 30
Units
o o o o o o
C/W C/W C/W C/W C/W C/W
The VSC7123 is designed to operate with a case temperature up to 95oC. The user must guarantee that the case temperature specification is not violated. With the thermal resistances shown in Table 7, the 10mm thermally-enhanced PQFP package can operate in still air ambient temperatures of 50oC [50oC = 95oC - 0.9W * 50 C/W]. The 14mm thermally-enhanced PQFP package can operate in still air ambient temperatures of 69oC [69oC = 95oC - 0.9W * 29 C/W]. The TQFP package can operate in a still air ambient temperature of 59oC [59oC = 95oC - 0.9W * 40 C/W]. If the ambient air temperature exceeds these limits, a form of cooling through a heatsink or an increase in airflow must be provided.
Moisture Sensitivity Level
This device is rated at a Moisture Sensitivity Level 3 rating with maximum floor life of 168 hours at 30C, 60% relative humidity. Please refer to Application Note AN-20 for appropriate handling procedures.
G52212-0, Rev 4.3 03/25//01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 17
L VE
O
Y C IT
TM
VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet
Data Sheet
VSC7123
Ordering Information
The part number for this product is formed by a combination of the device number and the package style.
VSC7123
Device Type 10-Bit Transceiver
xx
Package QN: 64-Pin, 14x14mm PQFP QU: 64-Pin, 10x10mm PQFP RD: 64-Pin, 10x10mm TQFP
Marking Information
The package is marked with three lines of text as shown in Figure 11 (QU package shown).
Figure 11: Package Marking Information
Pin 1 Identifier
Part Number DateCode
VSC7123QU ####AAAAA VITESSE
Package Suffix Lot Tracking Code (4 or 5 characters)
Notice
Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
Page 18
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52212-0, Rev 4.3 03/25/01

▲Up To Search▲

Price & Availability of VSC7123

	To Download VSC7123 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .